Instruction Set

(quick finder)

 

This document describes, as completely as I am aware of, the ARM instruction set. If, however, you are only interested in the instructions relating to programming under RISC OS, you may prefer to read the shorter quick finder document...

 

Processor types
ARM 2
ARM 3
ARMv2
ARM 2 or ARM 3
 
ARMv3 ARM6xx or ARM7xx
 
ARMv4 StrongARM
 
ARMv5 ARM9, XScale, etc
 
Floating Point Hardware or (usually) software floating point, from ARM 2 (software) to ARM7500FE (mostly hardware). No RISC floating point unit is entirely hardware, it is a balance between basic FP instructions in hardware, and more complex things (like RMF) in software.
 
VFP Vector Floating Point, in ARMv5 (etc) processors
 
Thumb 16 bit-ised version of ARM as an option in ARMv5 (etc) processors
 
For the full range, refer to the ARM Ltd documentation.

 

 

Instructions in bold are the core ARM instructions.
Instructions in italics are provided by the Floating Point Accelerator/Emulator.
Instructions in Dark Grey italics are miscellaneous ARMv5 instrctions.

Instructions in Dark Slate Grey italics are VFP or Thumb instructions.

 

Instruction
Meaning
Earliest CPU / Comments
 
ABS
Absolute Value
Floating Point 1
 
ACS
Arc Cosine
Floating Point 5
 
ADC
Add with Carry
-
 
ADC
Thumb: Add with Carry
Thumb
 
ADD
Add
-
 
ADD
Thumb: Add
Thumb
 
ADF
Add
Floating Point 1 3
 
ADR
Get address of object (within 4K)
This is an assembler pseudo-instruction
 
ADRL
Get address of object (beyond 4K)
This is an assembler pseudo-instruction
 
ALIGN
Set the program counter to the next word boundary
This is an assembler pseudo-instruction
 
AND
Logical AND
-
 
AND
Thumb: Logical AND
Thumb
 
ASL
Arithmetic Shift Left
This is an option, not an instruction
 
ASN
Arc Sine
Floating Point 5
 
ASR
Arithmetic Shift Right
This is an option, not an instruction;
available on Thumb.
 
ATN
Arc Tangent
Floating Point 5
 
B
Branch
-
 
B
Thumb: Branch
Thumb
 
BIC
Bit Clear
-
 
BIC
Thumb: Bit Clear
Thumb
 
BKPT
Thumb: Breakpoint
Thumb
 
BL
Branch with Link
-
 
BL
Thumb: Long Branch with Link
Thumb
 
BLX
Thumb: Branch with Link and Exchange
Thumb
 
BX
Thumb: Branch and Exchange
Thumb
 
CDP
Co-processor data operation
-
 
CDP2
CDP, non-conditional so more co-processor commands possible
ARMv5
 
CLZ
Count Leading Zeros
ARMv5
 
CMF
Compare floating point value
Floating Point 1 3
 
CMN
Compare negated values
-
 
CMN
Thumb: Compare negated values
Thumb
 
CMP
Compare values
-
 
CMP
Thumb: Compare values
Thumb
 
CNF
Compare negated floating point values
Floating Point 1
 
COS
Cosine
Floating Point 5
 
DCx
Define byte (B), halfword (W), word (D), string (S), or floating point (F) value.
Some assemblers allow DCFS, DCFD, etc for FP precision.
This is an assembler pseudo-instruction
 
DVF
Divide
Floating Point 1 3
 
EOR
Exclusive-OR two values
-
 
EOR
Thumb: Logical Exclusive-OR
Thumb
 
EQUx
Define byte (B), halfword (W), word (D), string (S), or floating point (F) value.
Some assemblers allow EQUFS, EQUFD, etc for FP precision.
This is an assembler pseudo-instruction
 
EXP
Exponent
Floating Point 5
 
FABS
VFP: Absolute
VFP
 
FADD
VFP: Addition
VFP
 
FCMP
VFP: Compare
VFP
 
FCVTDS
VFP: Single to Double
VFP
 
FCVTSD
VFP: Double to Single
VFP
 
FCPY
VFP: Copy [like MVF]
VFP
 
FDIV
VFP: Division
VFP
 
FDV
Fast Divide
Floating Point 1
 
FIX
Convert floating value to an integer
Floating Point 1 3
 
FLD
VFP: Load VFP registers
VFP
 
FLDMDB
VFP: Load multiple VFP registers, decr. before
VFP
 
FLDMIA
VFP: Load multiple VFP registers, incr. after
VFP
 
FLT
Convert integer to a floating value
Floating Point 1 3
 
FMAC
VFP: Multiply with Accumulate
VFP
 
FMDHR
VFP: Transfer ARM register to upper half of Double
VFP
 
FMDLR
VFP: Transfer ARM register to lower half of Double
VFP
 
FMRDH
VFP: Transfer upper half of Double to ARM register
VFP
 
FMRDL
VFP: Transfer lower half of Double to ARM register
VFP
 
FML
Fast multiply
Floating Point 1
 
FMSC
VFP: Multiply with Negate and Accumulate
VFP
 
FMRS
VFP: Transfer Single to ARM register
VFP
 
FMSR
VFP: Transfer ARM register to Single
VFP
 
FMUL
VFP: Multiply
VFP
 
FMRX
VFP: Transfer VFP system register to ARM register
VFP
 
FMSTAT
VFP: Transfer FPSCR flags to CPSR
VFP
 
FMXR
VFP: Transfer ARM register to VFP system register
VFP
 
FNEG
VFP: Copy Negative [like MVN]
VFP
 
FNMAC
VFP: Multiply with Deduct
VFP
 
FNMSC
VFP: Multiply with Negate and Deduct
VFP
 
FNMUL
VFP: Negative Multiply
VFP
 
FRD
Fast reverse divide
Floating Point 1
 
FSITO
VFP: Signed Integer to Float
VFP
 
FSQRT
VFP: Square Root
VFP
 
FST
VFP: Save VFP registers
VFP
 
FSTMDB
VFP: Save multiple VFP registers, decr. before
VFP
 
FSTMIA
VFP: Save multiple VFP registers, incr. after
VFP
 
FSUB
VFP: Subtraction
VFP
 
FTOSI
VFP: Float to Signed Integer
VFP
 
FTOUI
VFP: Float to Unsigned Integer
VFP
 
FUITO
VFP: Unsigned Integer to Float
VFP
 
LDC
Load from memory to co-processor
-
 
LDC2
LDC, non-conditional so more co-processor commands possible
ARMv5
 
LDF
Load floating point value
Floating Point 1 3
 
LDM
Load multiple registers
-
 
LDMIA
Thumb: Load multiple registers
Thumb
 
LDR
Load register (32 bit)
-
 
LDR
Thumb: Load register (32 bits?)
Thumb
 
LDRB
Load byte (8 bit) into register
-
 
LDRB
Thumb: Load byte (8 bit) into register
Thumb
 
LDRH
Load halfword (16 bit) into register
StrongARM
 
LDRH
Thumb: Load halfwit (boo!) into register
Thumb
 
LDRSB
Load signed byte (sign + 7 bit) into register
StrongARM
 
LDRSB
Thumb: Load signed byte (sign + 7 bit) into register
Thumb
 
LDRSH
Load signed halfword (sign + 15 bit) into register
StrongARM
 
LDRSH
Thumb: Load signed halfword (sign + 15 bit) into register
Thumb
 
LFM
Load multiple floating point values
Floating Point 1
 
LGN
Logarithm to base e
Floating Point 5
 
LOG
Logarithm to base 10
Floating Point 5
 
LSL
Logical Shift Left
This is an option, not an instruction;
available on Thumb.
 
LSR
Logical Shift Right
This is an option, not an instruction;
available on Thumb.
 
MCR
Co-processor register transfer (ARM to co-processor)
-
 
MCR2
MCR, non-conditional so more co-processor commands possible
ARMv5
 
MCRR
MCR, with two registers transferred at one time
ARMv5TE
 
MLA
Multiply with Accumulate
-
 
MNF
Move negated
Floating Point 1
 
MOV
Move value/register into a register
-
 
MOV
Thumb: Move value/register into a register
Thumb
 
MRC
Co-processor register transfer (co-processor to ARM)
-
 
MRC2
MRC, non-conditional so more co-processor commands possible
ARMv5
 
MRRC
MRC, with two registers transferred at one time
ARMv5TE
 
MRS
Move status flags to a register
ARM 6
 
MSR
Move contents of a register to the status flags
ARM 6
 
MUF
Multiply
Floating Point 1 3
 
MUL
Multiply
-
 
MUL
Thumb: Multiply
Thumb
 
MVF
Move value/float register into a float register
Floating Point 1 3
 
MVN
Move negated
-
 
MVN
Thumb: Move negated
Thumb
 
NEG
Thumb Negate
Thumb
 
NOP
Thumb: No Operation
Thumb
 
NRM
Normalise
Floating Point 1
 
OPT
Select assembly options
This is an assembler pseudo-instruction
 
ORR
Logical OR
-
 
ORR
Thumb: Logical OR
Thumb
 
PLD
PreLoaD
ARMv5
 
POL
Polar Angle
Floating Point 5
 
POP
Thumb: Pop registers from stack
Thumb
 
POW
Power
Floating Point 5
 
PUSH
Thumb: Push registers onto stack
Thumb
 
QADD
Add, saturating
ARMv5E
 
QDADD
Add, double saturating
ARMv5E
 
QDSUB
Subtract, double saturating
ARMv5E
 
QSUB
Subtact, saturating
ARMv5E
 
RDF
Reverse Divide
Floating Point 1
 
RFC
Read FP control register
Floating Point 1 4
 
RFS
Read FP status register
Floating Point 1 3
 
RMF
Remainder
Floating Point 2 3
 
RND
Round to integral value
Floating Point 2 3
 
ROR
Rotate Right
This is an option, not an instruction;
available on Thumb.
 
RPW
Reverse Power
Floating Point 5
 
RRX
Rotate Right with extend
This is an option, not an instruction
 
RSB
Reverse Subtract
-
 
RSC
Reverse Subtract with Carry
-
 
RSF
Reverse Subtract
Floating Point 1
 
SBC
Subtract with Carry
-
 
SBC
Thumb: Subtract with Carry
Thumb
 
SFM
Store Muliple Floating point values
Floating Point 1
 
SIN
Sine
Floating Point 5
 
SMLA
Signed Multiply with Accumulate of 16 bit * 16 bit values
ARMv5E
 
SMLAL
Signed Long (sign + 63 bit) Multiply with Accumulate
StrongARM
 
SMLAL
Signed Multiply with Accumulate of 16 bit * 16 bit values,
result is sign extended to 32 bits, then added to a 64 bit value.
ARMv5E
 
SMLAW
Signed Multiply with Accumulate of 32 bit * 16 bit values
ARMv5E
 
SMUL
Signed Multiply of 16 bit * 16 bit values
ARMv5E
 
SMULL
Signed Long (sign + 63 bit) Multiply
StrongARM
 
SMULW
Signed Multiply of 32 bit * 16 bit values
ARMv5E
 
SQT
Square Root
Floating Point 2 3
 
STC
Co-processor data transfer
-
 
STC2
STC, non-conditional so more co-processor commands possible
ARMv5
 
STF
Store floating point value
Floating Point 1 3
 
STM
Store multiple registers
-
 
STMIA
Thumb: Store multiple registers
Thumb
 
STR
Store a register (32 bit)
-
 
STR
Thumb: Store register (32 bit?)
Thumb
 
STRB
Store a byte (8 bit) from a register
-
 
STRB
Thumb: Store byte (8 bit)
Thumb
 
STRH
Store a halfword (16 bit) from a register
StrongARM
 
STRH
Thumb: Store halfword (16 bit)
Thumb
 
STRSB
Store a signed byte (sign + 7 bit) from a register
StrongARM
 
STRSH
Store a signed half-word (sign + 15 bit) from a register
StrongARM
 
SUB
Subtract
-
 
SUB
Thumb: Subtract
Thumb
 
SUF
Subtract
Floating Point 1 3
 
SWI
Cause a SoftWare Interrupt
-
 
SWI
Thumb: SoftWare Interrupt
Thumb
 
SWP
Swap register with memory
ARM 3
 
TAN
Tangent
Floating Point 5
 
TEQ
Test Equivalence (notional EOR)
-
 
TST
Test bits (notional AND)
-
 
TST
Thumb: Test bits
Thumb
 
UMLAL
Unsigned Long (64 bit) Multiply with Accumulate
StrongARM
 
UMULL
Unsigned Long (64 bit) Multiply
StrongARM
 
URD
Unnormalised round
Floating Point 1
 
WFC
Write FP control register
Floating Point 1 4
 
WFS
Write FP status register
Floating Point 1 3
 

 

  1. On the ARM7500FE, these FP instructions are provided by hardware.
  2. On the ARM7500FE, these FP instructions are provided by software.
  3. This FP instruction is required by IEEE (754-1985).
  4. These FP instructions are only provided by hardware floating point systems.
  5. These FP instructions are provided for backwards compatibility, and are emulated.

 

Instructions in bold are the core ARM instructions.
Instructions in italics are provided by the Floating Point Accelerator/Emulator.
Instructions in Dark Grey italics are miscellaneous ARMv5 instrctions.

Instructions in Dark Slate Grey italics are VFP or Thumb instructions.

Everything else are bits and pieces that were worth including, shift options and common assembler mnemonics...

Co-processor instructions are listed. However the ARM processors used in RISC OS machines do not support co-processors, and only the virtual co-processor functions present within the chip can be accessed. These provide facilities for setting up the ARM, cache, MMU, etc...

The Thumb instructions are a subset of the normal ARM instructions, designed to work in a 16 bit mode. This allows more code in less memory, and for cheaper memory subsystems to be used. It is a compromise between the ARM's 32 bit power, and cost-effectiveness. Before you scratch your head and think "Huh? But DIMMs are cheap!", remember life is rather different when we are talking of specialist embedded devices, ranging from spacecraft to mobile phones. Anyway, some instructions, like STR and MOV are duplicated for the Thumb instructions so there's no ambiguity.
The Vector Floating Point appears to be a superset of the hardware components of the original FPU. Things like POW and COS are not present, as they can be done with software assistance - it would not be in keeping with RISC principles to devote silicon to things like that.


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Copyright © 2004 Richard Murray