Instruction Set(quick finder) 
This is the 'shorter' quick finder, for programming under RISC OS. For a more complete look at the ARM instruction set, please refer to the complete quick finder document.
Instructions in bold are the core ARM instructions.
Instructions in italics are provided by the Floating Point Accelerator/Emulator.
Instruction  Meaning  Earliest CPU / Comments

ABS  Absolute Value  Floating Point ^{1}

ACS  Arc Cosine  Floating Point ^{5}

ADC  Add with Carry  

ADD  Add  

ADF  Add  Floating Point ^{1 3}

ADR  Get address of object (within 4K)  This is an assembler pseudoinstruction

ADRL  Get address of object (beyond 4K)  This is an assembler pseudoinstruction

ALIGN  Set the program counter to the next word boundary  This is an assembler pseudoinstruction

AND  Logical AND  

ASL  Arithmetic Shift Left  This is an option, not an instruction

ASN  Arc Sine  Floating Point ^{5}

ASR  Arithmetic Shift Right  This is an option, not an instruction.

ATN  Arc Tangent  Floating Point ^{5}

B  Branch  

BIC  Bit Clear  

BL  Branch with Link  

CDP  Coprocessor data operation  

CMF  Compare floating point value  Floating Point ^{1 3}

CMN  Compare negated values  

CMP  Compare values  

CNF  Compare negated floating point values  Floating Point ^{1}

COS  Cosine  Floating Point ^{5}

DCx  Define byte (B), halfword (W), word (D), string (S), or floating point (F)
value. Some assemblers allow DCFS, DCFD, etc for FP precision.  This is an assembler pseudoinstruction

DVF  Divide  Floating Point ^{1 3}

EOR  ExclusiveOR two values  

EQUx  Define byte (B), halfword (W), word (D), string (S), or floating point (F)
value. Some assemblers allow EQUFS, EQUFD, etc for FP precision.  This is an assembler pseudoinstruction

EXP  Exponent  Floating Point ^{5}

FDV  Fast Divide  Floating Point ^{1}

FIX  Convert floating value to an integer  Floating Point ^{1 3}

FLT  Convert integer to a floating value  Floating Point ^{1 3}

FML  Fast multiply  Floating Point ^{1}

FRD  Fast reverse divide  Floating Point ^{1}

LDC  Load from memory to coprocessor  

LDF  Load floating point value  Floating Point ^{1 3}

LDM  Load multiple registers  

LDR  Load register (32 bit)  

LDRB  Load byte (8 bit) into register  

LDRH  Load halfword (16 bit) into register  StrongARM

LDRSB  Load signed byte (sign + 7 bit) into register  StrongARM

LDRSH  Load signed halfword (sign + 15 bit) into register  StrongARM

LFM  Load multiple floating point values  Floating Point ^{1}

LGN  Logarithm to base e  Floating Point ^{5}

LOG  Logarithm to base 10  Floating Point ^{5}

LSL  Logical Shift Left  This is an option, not an instruction; available on Thumb. 
LSR  Logical Shift Right  This is an option, not an instruction; available on Thumb. 
MCR  Coprocessor register transfer (ARM to coprocessor)  

MLA  Multiply with Accumulate  

MNF  Move negated  Floating Point ^{1}

MOV  Move value/register into a register  

MRC  Coprocessor register transfer (coprocessor to ARM)  

MRS  Move status flags to a register  ARM 6

MSR  Move contents of a register to the status flags  ARM 6

MUF  Multiply  Floating Point ^{1 3}

MUL  Multiply  

MVF  Move value/float register into a float register  Floating Point ^{1 3}

MVN  Move negated  

NOP  No OPeration  usually outputs 'MOV R0, R0'  This is an assembler pseudoinstruction

NRM  Normalise  Floating Point ^{1}

OPT  Select assembly options  This is an assembler pseudoinstruction

ORR  Logical OR  

POL  Polar Angle  Floating Point ^{5}

POW  Power  Floating Point ^{5}

RDF  Reverse Divide  Floating Point ^{1}

RFC  Read FP control register  Floating Point ^{1 4}

RFS  Read FP status register  Floating Point ^{1 3}

RMF  Remainder  Floating Point ^{2 3}

RND  Round to integral value  Floating Point ^{2 3}

ROR  Rotate Right  This is an option, not an instruction; available on Thumb. 
RPW  Reverse Power  Floating Point ^{5}

RRX  Rotate Right with extend  This is an option, not an instruction

RSB  Reverse Subtract  

RSC  Reverse Subtract with Carry  

RSF  Reverse Subtract  Floating Point ^{1}

SBC  Subtract with Carry  

SFM  Store Muliple Floating point values  Floating Point ^{1}

SIN  Sine  Floating Point ^{5}

SMULL  Signed Long (sign + 63 bit) Multiply  StrongARM

SQT  Square Root  Floating Point ^{2 3}

STC  Coprocessor data transfer  

STF  Store floating point value  Floating Point ^{1 3}

STM  Store multiple registers  

STR  Store a register (32 bit)  

STRB  Store a byte (8 bit) from a register  

STRH  Store a halfword (16 bit) from a register  StrongARM

STRSB  Store a signed byte (sign + 7 bit) from a register  StrongARM

STRSH  Store a signed halfword (sign + 15 bit) from a register  StrongARM

SUB  Subtract  

SUF  Subtract  Floating Point ^{1 3}

SWI  Cause a SoftWare Interrupt  

SWP  Swap register with memory  ARM 3

TAN  Tangent  Floating Point ^{5}

TEQ  Test Equivalence (notional EOR)  

TST  Test bits (notional AND)  

UMLAL  Unsigned Long (64 bit) Multiply with Accumulate  StrongARM

UMULL  Unsigned Long (64 bit) Multiply  StrongARM

URD  Unnormalised round  Floating Point ^{1}

WFC  Write FP control register  Floating Point ^{1 4}

WFS  Write FP status register  Floating Point ^{1 3}

Instructions in bold are the core ARM instructions.
Instructions in italics are provided by the Floating Point Accelerator/Emulator.
Everything else are bits and pieces that were worth including, shift options and common assembler mnemonics...
Coprocessor instructions are listed. However the ARM processors used in RISC OS machines do not support coprocessors, and only the virtual coprocessor functions present within the chip can be accessed. These provide facilities for setting up the ARM, cache, MMU, etc...