MDFS hardware

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The hardware

The MDFS uses a Z80 processor clocked at 6MHz. The Econet interface is an unusual arrangement with the serial I/O chip; instead of using a 6854 ADLC.

To the left of the processor is an 8K EPROM which contains the base services and boot routine for the server. Consider this similar to the BIOS in a PC.

There is 256K RAM onboard, half of which is taken by the server code when loaded.

Finally, the server provides a host of interface options; serial and parallel printer, two floppy interfaces (giving four drives in total), and on-board SCSI.


The Z80 SIO?

Actually, the Z80 Serial I/O chip (SIO) is capable of doing pretty much everything that the 6854 ADLC can do. In addition, the chip has the ability to match, itself without processor involvement, the first byte of the frame and know whether to accept or discard the frame according to the result of this match. With the 6854, it passes the address (net/station) on to the host which should examine the data and decide whether to accept the data, or 'discontinue' for the remainder of the frame. This can take places dozens of times each second.
Not just that, but the SIO can calculate CRCs for received data, and operate in SDLC mode (with flag filling).
Perhaps this is how a 6MHz Z80 (which is arguably slower overall than a 2MHz 6502) can appear to be so powerful and fast.


Circuit layout

Click here for a diagram (not a schematic) of the MDFS server.
It is a large image, so those of you with lower-end machines may prefer to download the original DrawFile, click here for that.



All of this information has been made by observation only. If anybody has a circuit diagram or service guide for the MDFS, please let me know...

Copyright © 2008 Rick Murray