heyrick1973 -at- yahoo -dot- co -dot uk
JTAG - figuring out a Wiggler clone
I was sent this a long time ago. Just the device and a short length of 20-way IDC cable to plug into it.
Since there was a good chance this is a Wiggler clone, so I plugged it into my parallel port (now that I have a computer with a parallel port!) and loaded up OCD Commander which seemed to work, just some errors about no JTAG device being detected, which is logical...
What has me confused is that there are loads of photos and schematics of Wiggler clones based upon the 74HC244 device, but they all use one of them. This interface uses two. Is this some sort of double buffering?
As I have no information on it, all I know is what the JTAG 20 pin pinout ought to be (assuming the older ARM9 style "traditional" pinout), how Wiggler devices are communicated with (by looking at some random schematics to determine the parallel port pinning), and a diagram of the logic gates inside the 74HC244.
So, after some poking around with a multimeter...
- The evens first, we can do them all together: Pin 2 does not appear to be connected. Pins 4 to 18 are all grounded. Pin 20 is grounded via a 22 ohm resistor, no idea why.
- JTAG pin 1 is connected to the VCC of the upper chip (in picture above), so the target device powers its own buffer chip, which will mean also that the signal levels presented will be at the same logic level as the target board (probably 3.3V).
Conversely, the VCC of the lower chip is connected to parallel port D7 - so if D7 is always asserted, then the parallel port buffer chip will output data at the same signal level as the parallel port (instead of likely ~3.3V).
- JTAG pin 3 is ultimately (via both chips) connected to parallel D4.
This is consistent with JTAG !TRST.
!TRST (red in the annotated diagram) is an inverted (active LOW) input that is used to reset the state of the JTAG test logic.
- JTAG pin 5 passes both ICs to connect to parallel port D3.
This is consistent with JTAG TDI.
TDI (green in the annotated diagram) is the serial data input.
- JTAG pin 7 passes both ICs to connect to parallel port D1.
This is consistent with JTAG TMS.
TMS (blue in the diagram) controls which the test logic state machine is in.
- JTAG pin 9 passes both ICs to connect to parallel port D2.
This is consistent with JTAG TCK.
TCK (yellow in the diagram) is a 'clock' that latches data from TDI and TMS in the rising edge, and TDO on the falling edge. Note it has a capacitor to ground to terminate (you can see this as the lump to the left of D3's pin).
- JTAG pin 11 passes both ICs (in gating in the reverse direction, so this is an output pin) to arrive at parallel ACK.
This seems consistent with RTCK for devices that support it.
RTCK, or ReTurn ClocK, (magenta in the diagram) is sometimes used to synchronise clock pulses for high speed JTAG where TCK will not advance until RTCK has been asserted (meaning devices all synchronised). I doubt this will be an issue for a parallel port widget. ☺
- JTAG pin 13 passes both ICs (in gating in the reverse direction, so this is an output pin) to arrive at parallel !BUSY.
This is consistent with JTAG TDO.
TDO (cyan in the diagram) is the output of the serial data. How it works is TDI data passes to TDO which is connected to the TDI of the next device in the chain, and data is 'clocked' in and out using a predefined protocol (otherwise known as magic).
- JTAG pin 15 is connected to a transistor gated by parallel D0.
This is consistent with JTAG !SRST.
!SRST (orange in the diagram) is an inverted (active LOW) signal that can be used to force the target board into a reset.
- JTAG pin 17 is connected to a transistor gated by parallel D5.
Unknown - supposed to be JTAG DBGRQ, but I don't see any schematics using this.
Not that it matters, because...
- JTAG pin 19 is connected to the middle pin of the three large pads above the upper chip.
There appears to be no further connection, so I'm guessing it is a link to select how JTAG DBGACK would be handled if it were actually connected to something.
- Nothing to do with JTAG, but parallel D6 is connected to parallel ERROR, which is how the Wiggler interface identifies itself.
This makes our connections as follows, which does indeed fit the traditional (ARM9 generation) JTAG pinning:
VCC O< O n/c
(D4) !TRST O O GND
(D3) TDI O O GND
(D1) TMS O O GND
(D2) TCK O O GND
(ACK) RTCK O O GND
(!BUSY) TDO O O GND
(D0) !SRST O O GND
-- O O GND
n/c O O GND (via 22 ohm)
Can anybody find something wrong with this, or does that look good to go?
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Last read at 16:57 on 2019/01/21.
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