The ARM family
(Work in progress.)
Revision as of 03:52, 28 August 2011
The ARM family is not simple to figure out. ARM cores don't match architecture numbers, letter suffixes are not always straightforward, and while looking for information on the ARM926 core in my PVR, the only thing I can say for certain is it is an ARM9 processor, and apparently nobody knows what the '26' suffix means. Um...
So here's a potted history of the ARM family.
It started with the ARM2. There were some ARM1s, but not many. It was the Acorn Archimedes that arrived in the world with an ARM2 onboard. Then came the ARM3.
There never was an ARM4 or ARM5.
By this time, Apple, DEC, and Intel got on board. Thus gave birth to the ARM6 and ARM7 processors, in a variety of guises. These were used in the RiscPC range, among other devices. DEC developed the StrongARM, and as part of a settlement this was given to Intel who refined it and created their own XScale processor which had since been passed on to somebody else. By the way, an ARM8 did exist and was to be an upgrade for the RiscPC, but it never went anywhere as the StrongARM blew it out of the water, so to speak.
ARM(the company)'s fortunes took a turn for the better with the release of the ARM7TDMI - which meant Thumb, Debug, Multiplier, ICE - for it offered Thumb 16 bit instruction support, JTAG and on-chip JTAG debugger support. It has been widely deployed in embedded applications.
Now, hold your breath.
ARM design and licence cores, not processors. So the ARM 1 is architecture ARMv1, while ARM2 and ARM3 are architecture ARMv2; even if the difference between an ARM2 and an ARM3 is greater than that of an ARM2 compared to an ARM1.
The ARM6 and ARM7 are ARMv3. The ARM7TDMI is ARMv4(T) while the ARM7EJ is ARMv5(TEJ). The StrongARM and ARM8 are ARMv4 as well. The ARM9 is ARMv5, except for the ARM9TDMI which is ARMv4(T). The ARM11 is ARMv6.
After that point, everything is called Cortex. There are three families of Cortex. There is the Cortex-A aimed at application situations (this means it has an MMU), the Cortex-R aimed at real-time applications (extremely low latency), and a greatly restricted Cortex-M for microcontroller applications (may be Thumb only, few instructions, tiny pipeline) where ARM will give you "32 bit power at an 8 bit cost", to wean people away from PICs and AVRs and the like. Now I should point out that there is no hint of correlation in the suffix numbering. A Cortex-A3 is not like a Cortex-R3 or even remotely like a Cortex-M3. As it happens, only the M3 exists (A3 and R3 do not). There are holes in the numbering. They are all ARMv7 except the M0 which is ARMv6.
Note, incidentally, the Cortex suffix... A... R... M...
Let's take it a stage further. Thumb. A 16 bit reduced version of the ARM instruction set, right? Was that Thumb, Thumb2 (with some 32 bit instructions), or ThumbEE (?)?
To say this is all rather complicated would be an understatement.
There is a complete list on the other Wiki at http://en.wikipedia.org/wiki/List_of_ARM_microprocessor_cores
Ancient ARM, as used in the Acorn desktop computers, operates in the original mode where the Program Counter was 24 bits (effectively 26 bit as instructions are word aligned) with the upper eight bits being processor status and flags, and the lowest two bits providing the processor mode. They are all, with the exception of the StrongARM, are von Neumann architecture, meaning that the cache (if one exists) is a combined instruction and data cache.
All versions of RISC OS until the Castle RISC OS 5 for the Iyonix, worked in 26 bit mode. The ARM6, ARM7, and StrongARM processors were capable of 26 bit operation for compatibility.
No current processor supports the old 26 bit mode, these are legacy processors in the same vein as the 80386...
Contemporary ARM is a hard call. There are processors capable of running a desktop OS, but that isn't really where the ARM excels. The ARM excels in two areas - those who want a usable fairly feature-packed device that is light on battery consumption, and those who want a powerful and capable embedded system processor.
Therefore, you will find most Android mobile phones run on ARM, as does the Apple iPod/iPhone range. Numerous routers, printers, harddiscs, etc run ARM. However you can also get a Thumb-only ARM with a piddling amount of memory (something like 8KiB SRAM and 64KiB Flash) and a heap of I/O pins, which might sound like a bit of a joke, but it'd be perfectly suitable for microwaves, washing machines, bread makers, and so on.
This, therefore, presents a huge problem when talking contemporary ARM. We can say the later processors switched to Harvard architecture (separate data/instruction caches), we can say some of them have as much as a 13 stage pipeline (that's a lot in ARM terms). We can also say that some offer NEON DSP-like instructions, of vector floating point, or... but this would only be looking at one part of a very diverse family.
Perhaps the best way to think of it is that up to the ARM11, it was the ARM microprocessor going from strength to strength. Then following The Great Divide, when everything became a Cortex of some description, the ARM diversified. Massively.
The ARM family
The ARM family is described according to its base architecture version.
ARMv1 and ARMv2
The ARM1 is a fairly little-known processor that was where it all started. It was fitted on expansion and co-processor modules as, at the time, no suitable computer existed. Actually, prior to the creation of the chip in silicon, a simulation was written in BASIC. Now that would be code worth looking at!
After using the ARM1 system to design the support chips (IOC, MEMC, VIDC), The ARM Chipset went together to power the original Acorn Archimedes. Sadly the supplied OS was a bit crap, but when RISC OS 2 came along, people started to take notice.
In more technical terms, the 8MHz ARM2 improved upon the ARM1 by implementing integer multiply in silicon and providing a co-processor interface mechanism for the elusive floating point accelerator.
The next iteration of the ARM processor came in the form of the ARM3. Offering a 4KiB unified cache, plus increased clock speeds (usually 25MHz, although some 33MHz parts exist), it was compatible enough for a carrier board to be designed to plug in where an ARM2 used to be, giving an older machine an instant resurrection as something new.