The TST instruction allows you to test either if one or more bits of a register are clear, or at least one bit is set. The internal operation is an AND of the two operands.
Operand 1 is a register, operand 2 may be a register, shifted register, or an immediate value (which may be shifted).
There is no S bit, it is implied. The N, Z, and C flags are updated as usual (N - result bit 31, Z if result zero, C is shifter carry out). V is not updated.
TST is important in conditional execution and decision making.
There is also a Test Equivalence instruction for comparing values without affecting V.
TST <op 1>, <op 2>
<flags> = op_1 AND op_2 ; result is not stored, only flags updated
; Did our chip fire this IRQ? LDRB R0, [R3, #StatusFlags] ; load status flags TST R0, #(1<<7) ; is b7 set? BEQ OurInterruptHandler ; yes, so deal with interrupt
TSTP in 26 bit modes
TSTP is used, in 26 bit modes, to write values to R15 status bits. For example, to return from a privileged mode to User mode, we would preserve the flags and write them to PC like this:
MOV R0, #(63<<26) ; set mask for current flag bits TSTP R0, #0 ; update flags in PC
This works because TST performs an AND function, so instead of passing the flag bits we want to set or unset, we pass a mask of bits we want left alone.
Care must be taken not to access any banked registers (R8+) following the use of TSTP to change processor mode. It is usual to follow such a TSTP with a dummy instruction (MOV R0, R0) for this reason.
TSTP should NOT be used in 32 bit modes. Use [MSR] instead.
The instruction bit pattern is as follows:
|31 - 28||27||26||25||24 - 21||20||19 - 16||15 - 12||11 - 0|
|condition||0||0||I||1 0 0 0||1||op_1||0 0 0 0||op_2/shift|