Revision as of 17:52, 1 September 2011
|Function||SWaP register with memory|
|ARM family||ARMv3 (and ARMv2as (ARM3))|
While the ARM is a Load/Store architecture, there is one significant and important exception. That exception is the use of a semaphore which must be read from and/or written to memory in one atomic cycle (so that, for instance, an interrupt cannot get between reading and writing).
SWP will swap a word between register(s) and memory as follows: There is an address and two values, an original data and loaded data.
This instruction will load a word from <address> and remember it. The contents of register <original> are then written to the location pointed to by <address>. The remembered word is then placed in <loaded> (it does not overwrite the original data).
SWP <loaded>, <original>, [<address>]
<temp> = LDR [<address>, 4] STR [<address>, 4] = <original> <loaded> = <temp>
SWP R0, R1, [R2] ; Write R1 to location pointed to by R2 and ; place original contents of that address in R0
- If <loaded> and <original> are the same, the data in register and memory swapped.
- It is not possible to read a semaphore with SWP - you should LDR from the address.
- If the address is not word aligned, things will go wrong (CPUs without an MMU will rotate right the value, CPUs with an MMU will fault).
- None of the registers specified can be R15.
The instruction bit pattern is as follows:
|31 - 28||27 - 22||21 - 20||19 - 16||15 - 12||11 - 8||7 - 4||3 - 0|
|condition||0 0 0 1 0 0||0 0||<dest>||<load>||0 0 0 0||1 0 0 1||<value>|