|Function||Logically AND two values|
AND[S] : bitwise And
AND will perform a logical AND between the two operands, placing the result in the destination register; this is useful for masking the bits you wish to work on.
If the S bit is set (ANDS), the N and Z flags are set according to the result, the C flag is set according to the shift (if used), and the V flag remains unaltered.
AND is useful for masking bitfields in order to extract only the part that is necessary. For example, if the lower two bits contain flags, ANDing with 3 will keep those flag bits and discard any other data.
AND<suffix> <dest>, <op 1>, <op 2>
dest = op_1 AND op_2
AND sets the result bit only if both of the input bits are set.
|op_1 bit||op_2 bit||Result bit|
AND R0, R0, #3 ; Keep bits zero and one of R0, discard the rest. ANDS R0, R0, #3 ; As above, but also updates status flags
Demonstrating AND. We set up and pass a value in R1 (B%) and a mask in R2 (C%). The assembly code is called, which places the result in R0, which is thus returned and displayed.
DIM code% 16 P% = code% [ OPT 2 AND R0, R1, R2 ; R0 = R1 AND R2 MOV PC, R14 ] A% = 0 B% = 255 : REM Value to mask C% = %1111 : REM Bitmask PRINT "Result is " + STR$(USR(code%))
Demonstrating ANDS. We will take a value in R1 (B%), a mask in R2 (C%), and perform the operation. If the result is non-zero, we say so and print what the result is. If the result is zero, we say so. As it is non-trivial to pass flags back to BASIC on all types of ARM, all of the output is performed directly within the assembler code.
DIM code% 128 FOR loop% = 0 TO 2 STEP 2 P% = code% [ OPT loop% ; Print introduction message ADR R0, resultis SWI "OS_Write0" ; Perform the operation and test result ANDS R0, R1, R2' BEQ ifequal ; if result is non-zero, we do this ADR R1, resultis ; reuse this memory MOV R2, 11 SWI "OS_ConvertCardinal4" ADR R0, notequal SWI "OS_Write0" ADR R0, resultis SWI "OS_Write0" MOV PC, R14 .ifequal ADR R0, isequal SWI "OS_Write0" MOV PC, R14 .resultis EQUS "Result is " + CHR$(0) ALIGN .notequal EQUS "non-zero, is: " + CHR$(0) ALIGN .isequal EQUS "zero" + CHR$(0) ALIGN ] NEXT A% = 0 B% = 255 : REM Value to mask C% = %1111 : REM Bitmask CALL code%
To see these in action, the simplest method is to alter B% to 240 (%11110000).
The instruction bit pattern is as follows:
|31 - 28||27||26||25||24 - 21||20||19 - 16||15 - 12||11 - 0|
|condition||0||0||I||0 0 0 0||S||op_1||dest||op_2/shift|
Note: If the I bit is zero, and bits 4 and 7 are both one (with bits 5,6 zero), the instruction is MUL, not AND.